In current semiconductor integrated circuit devices, a multilayer interconnection structure has been used to interconnect among semiconductor elements. In ultrafine and ultra high-speed semiconductor devices, in order to reduce the problem of signal delay (RC delay), a low-resistance copper (Cu) pattern is used as a wiring pattern.
In order to form a copper wire, a so-called damascene method or dual-damascene method has been used. The damascene method is a method of forming a wire in which a Cu layer is buried in a wire groove or a via hole formed in an interlayer insulating layer using chemical mechanical polishing (CMP).
When the Cu wire is formed, a diffusion-reducing barrier is formed to reduce the diffusion of Cu atoms into an interlayer insulating layer. For the diffusion-reducing barrier, in general, refractory metals, such as tantalum (Ta), titanium (Ti), and tungsten (W), and conductive nitrides of the above refractory metals have been used.
However, the above materials have a higher resistivity than that of Cu; hence, in order to further decrease the wiring resistance, the thickness of the diffusion-reducing barrier may be decreased as small as possible. Accordingly, Japanese Laid-open Patent Publication No. 2007-59660 discusses a technique that a Cu—Mn alloy is used instead of the diffusion-reducing barrier. The reason for this is that MnSixOy is formed in a self-alignment manner at the interface between an interlayer insulating layer and a Cu wire by a reaction of Mn with O2 and Si, which are contained in the interlayer insulating layer, and that Mn oxides function as a diffusion-reducing layer. However, at the interface between the interlayer insulating layer and the Cu wire, when Mn which is not allowed to react with O2 contained in the interlayer insulating layer dissolves in the Cu wire, the resistance of the Cu wire may increase.